1. Field of the Invention
The invention relates to electrical testing of printed circuit boards, multi-chip modules, and other planar electrical interconnect devices.
2. Background of the Invention
Numerous problems arise in testing electrical interconnect devices. These devices require simultaneously contacting a set of electrical test points distributed in a nonuniform pattern across the surface of the electrical interconnect device (the xe2x80x9ctest point gridxe2x80x9d). The test point grid is typically planar. The test points must be connected electrically to a regular, planar grid of measurement contact points such than an isolated, conductive circuit path is created to each test point. A xe2x80x9cmeasurement contact arrayxe2x80x9d is held parallel to the test point grid at a distance of a few inches from the surface of the test point grid.
For illustrative purposes in the remainder of this disclosure, a printed circuit board (PCB) will be used as the exemplary item presenting the plane of points to be tested. The points to be tested on a PCB are positioned to match terminals of electrical components that will eventually be soldered to the PCB. Electrical components have their terminal connection points positioned in various patterns. The connection points are often more closely spaced than the spacing between, or pitch of, the contact points in the measurement contact array.
FIG. 1 shows a view perpendicular to the two planes (test point grid and planar contact array) for a small section of an exemplary PCB. The large crosses 22 depict measurement points on a measurement contact array 20. The solid rectangles depict test points 24 on the surface of the PCB (the test point grid). In this example, the density parallel to the rows of test points 24 is four times greater than the pitch of the measurement contact points 22.
A method of implementing the conductive path in common use in the electrical test industry is to employ rigid or semi-rigid metal xe2x80x9cprobe pinsxe2x80x9d to contact the PCB test points. A distal end of the probe pin is held in mechanical contact with a test point on the PCB and the other end is held in mechanical contact with one element of the measurement contact array. A typical probe pin has a length of 3 inches and a diameter of 0.020 inches, providing a very high aspect ratio. Longer or shorter pins are sometimes used.
Defining which measurement contact point of the measurement contact array will be connected to a particular test point by a probe pin is referred to as xe2x80x9cassigningxe2x80x9d a probe pin to a test point. The particular set of all assigned probe pins for an exemplary PCB is referred to in the art as a xe2x80x9cpin assignment pattern.xe2x80x9d
Because the pattern of test points on the PCB surface does not present a regular X-Y coordinate grid, and because the area-density of these test points is greater than the measurement points of the measurement contact array, it becomes necessary to angle or lean most or all of the probe pins away from vertical in order that all of the test points be contacted simultaneously. This is called xe2x80x9cdeflectionxe2x80x9d in the trade, even though the probe pin itself is not bent. The set of all probe pins defined by a pin assignment pattern, plus the insulating mechanical structure that supports and constrains these probe pins are assembled into a mechanical appliance referred to in the trade as an xe2x80x9celectrical test fixture.xe2x80x9d
FIG. 2a shows examples of the key elements of interest related to an electrical test fixture 28. Three example test points A, B and C are shown on test point grid 26. These points A, B and C are connected to three measurement contact points 22a, 22b and 22c by three deflected probe pins 30a, 30b and 30c. The amount that a probe pin 30 deflects away from vertical to the plane containing the measurement contact array 20 and test point grid surfaces 26 is measured as a linear distance shown as d in FIG. 2b. This distance d is the sine of the angle of deflection a multiplied by the length of the probe pin. Measuring deflection as a distance rather than as an angle is customary in the trade. This deflection assumes a straight probe 30, and that the measurement contact array 20 is parallel to the test point grid 26.
Constructing a test fixture 28 requires that a pattern of probe pins 30 be produced which simultaneously connect each test point A, B or C to a unique measurement contact point 22 without any two pins 30a, 30b or 30c coming in contact with one another. To construct a usable test fixture 28, the pins 30 must be mechanically supported in three dimensional space such that they cannot move in any direction parallel to the surface of the planes containing the measurement contact array 20 or the test point grid 26.
An ideal fixture support structure would be constructed from a solid block of insulating material of thickness equal to the distance separating the test point grid from the measurement contact array. One hole would be bored through the insulating block for each pin. The bored hole may describe a straight line, an arc, or a combination of the two. All holes that emerge from the top side of the block will have (x,y) locations that are a multiple of the grid pitch, aligning with the measurement contact array. The holes that emerge from the bottom (PCB) side of the block will match the unique pattern of test points on the test point grid.
By placing the insulating block on top of the PCB to be tested, inserting probe pins into each hole, placing the measurement contact array on top of the test fixture structure, and applying a compressive force to the entire stack, the desired electrical circuit paths connecting each test point are realized.
In current industry practice, the single, solid block of insulating material is replaced by 3 to 10 parallel plates of insulating material, separated by spacer posts at the periphery and bolted together. This assembly of plates and spacers occupies the identical volume as the solid block of the ideal fixture. It constrains the pins in an analogous manner, using one hole per pin per plate. A typical test fixture 28 will contain between 5,000 and 25,000 probe pins.
Because probe pins 30 can deflect in any direction, a multiplicity of different probe pin assignment patterns may be chosen to build test fixtures 28 for a given printed circuit board. All such fixtures 28 must have the same pattern of holes on the bottom surface for contacting the test points A, B or C in the test point grid 20. However, some or all of the probe pins 30 will be connected to different points on the measurement contact array 20. Any of the multiple probe pin patterns define valid test fixtures for a given PCB as long as all test points are connected to a unique measurement contact point.
However, certain pin assignment patterns will provide superior electrical performance to others. A commonly used measure by which to judge the relative quality of several fixtures designed for the same PCB is to compare the deflections of the most deflected pin or pins within each fixture. Given two test fixtures for the same PCB, the one with the lower maximum deflection is considered superior to those in the trade.
There is a sound physical reason for using maximum deflection as a predictor of fixture performance. As its deflection rises, the ability of a probe pin to make a reliable electrical connection to its test point decreases. At some critical deflection, electrical contact is broken. An empirical deflection limit is typically set, below which experience has shown that probe pins operate reliably. The further below this limit all pins of a fixture are deflected, the more reliable a fixture becomes, although below a certain limit, little improvement in reliability is seen.
Current Methods for Test Fixture Pin Assignment
Developing a probe pin pattern to contact 25,000 points simultaneously without shorting any two of the probe pins together is a difficult problem. Even with computer assistance, technicians skilled in the art of fixture design require from several hours to an entire day to produce a successful fixture probe pin assembly.
To successfully design a valid probe pin pattern for the construction of an electrical test fixture, the following three requirements must be met:
1. Every test point in the test point grid must be connected using a probe pin to a unique measurement contact point within the measurement contact array.
2. No probe pin may touch or otherwise interfere spatially with another probe pin.
3. No probe pin may exceed the maximum deflection limit set for the fixture.
Designing a test fixture becomes difficult when the maximum deflection for probe pins rises above 10 to 15 percent of the length of the probe pin. Computer systems can be used to aid in the construction of probe pin patterns for test fixtures. But even with computers significant difficulties arise because the pin assignment task involves searching through an exponentially large set of possible assignment patterns. For example, suppose the maximum deflection allowed for a fixture""s pins places ten measurement contact points within range of each test point. If there are 10,000 points to be tested, the number of pin assignment permutations is on the order of 1010,000 (the numeral 1 followed by 10,000 zeros).
This large number of permutations precludes using any known general purpose computer to sequentially examine each permutation. Since the vast majority of these permutations will be found to violate one or more of the three rules presented above, it would take an infeasible amount of time to search without expert guidance.
Because an exhaustive search is infeasible, current software algorithms do not revisit (or revisit a finite, small number of times) a probe pin once it has been assigned. The current processes examine each test point once and assign a pin. Since such systems do not know in advance whether the pin assignment permutation pattern they are constructing will be a successful one, they invariably reach a situation where there are no unused measurement contact points within the vicinity of an untested test point. Current technology software algorithms choose from two alternatives:
1. The software halts without assigning pins to contact all test points.
2. The software assigns pins to all test points, but uses a deflection greater than the allowed maximum, or greater than that desired by the operator.
In either case, a human expert must step in and correct or guide the probe pin assignment. The human operator intervenes by removing the probe pins at and surrounding the blocked area and then manually assigning pins for the difficult test points.
The present invention provides a fully automatic means for developing a pin assignment pattern for electrical test fixtures employed in testing printed circuit boards and other planar electrical interconnect devices including, but not limited to, multi chip modules and hybrid packages. For all but very simple devices with fewer than about 1,000 pins and deflections under about 0.2 inches, the pin assignment patterns and pin arrangements produced by the invention display a lower maximum probe pin deflection than pin assignment patterns designed by human experts, whether aided or unaided by any existing software algorithms.
The present invention offers the following improvements over the current state of the art in electrical test fixture pin assignment by the novel ability to direct its search of the exponentially large pin assignment search space. The pin deflection is minimized by always working outward from the most difficult points to better distribute the deflection, and advantageously, to equalize the deflection at the outward frontier of the assignment process. Much like the ripples that radiate out at equal velocity in all directions from a pebble dropped in a pond, the pins at the perimeter of the pin assignment process for a difficult area are iteratively adjusted to have approximately equal deflection.
Concentrating the search at the perimeter of difficult areas also reduces the number of patterns that must be considered. Continually equalizing the deflection at the perimeters of difficult areas also reduces the number of patterns that must be considered.
The invention provides a deterministic method of predicting and continuously updating which test points on the test point grid surface are currently most difficult to contact with a probe pin. The invention is able to use this computation of difficulty to provide an ordering for assigning probe pins to test points.
The invention searches heuristically for alternate test point-to-measurement contact point pin assignment patterns when a dead-end is reached. The invention is able to backtrack out of a dead-end, try alternate patterns, and remember all patterns tried in order to avoid falling into an infinite loop. The invention is able to remember which configurations have been tried, and intelligently search hundreds of thousands of combinations without requiring guidance of a human operator.
The combination of the above capabilities enables the invention to efficiently sort through the exponentially large set of pin assignment patterns and locate a pattern with suitably low maximum probe pin deflection. The efficiency provided by the invention enables this automatic, directed search to be done in a reasonable time on current technology digital computer work stations. This is in contrast to standard, non-heuristic search techniques generally used by others, including software algorithms, all of which have proved unable to handle the exponential search space involved in electrical test probe pin assignment.
This invention involves a process for creating a pin assignment for a test fixture for electrical interconnect devices. A difficulty rating is determined for each test point on an electrical interconnect device. The difficult areas are assigned the pins on a test grid, with the difficulty rating of adjacent test points being iteratively determined as the process continues. If a pin cannot be assigned because of conflicts, one or more adjacent test points are reassigned pins, with the difficulty metric being recalculated with each change and with pins being reassessed and reassigned. When all test points are assigned a pin, the pins are checked to see if they interfere with each other, and further iterations may result.